Correlated Double Sampling: The Art of Noise Cancellation in Image Sensors |
Executive Summary |
This article provides a comprehensive exploration of Correlated Double Sampling (CDS), the essential noise reduction technique that enables image sensors in barcode readers to deliver clean, reliable signals. We examine how CDS cancels the reset noise and fixed-pattern noise that would otherwise corrupt the tiny signals from CCD and CMOS sensors, ensuring accurate barcode decoding. Rather than focusing on abstract theory, we ground every concept in concrete design examples and real patent disclosures from industry leaders including Texas Instruments, Toshiba, and various other pioneering companies. We explore the fundamental principle of sampling and subtracting reset and signal levels, the detailed circuit architectures with capacitors and switches, the challenges of high-frequency noise and reference voltage shifts, and the innovative solutions developed to overcome these challenges. The article covers both the fundamental principles and the practical implementation details that make CDS the cornerstone of modern image sensor readout. The closing summary synthesizes the key lessons and offers practical guidance for anyone designing or selecting CDS circuits for barcode reading applications. |
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Chapter 1: The Noise Problem in Image Sensors |
The image sensor at the heart of a barcode reader is a marvel of engineering. It converts light into electrical charge, capturing the pattern of bars and spaces that encodes the barcode data. But this conversion is not perfect. The sensor introduces noise --- unwanted variations in the signal that can corrupt the barcode pattern and make decoding difficult or impossible. |
There are several sources of noise in an image sensor. The most significant is reset noise. Each pixel in the sensor must be reset before it can collect light. This reset operation leaves a random amount of charge on the pixel, which appears as a fixed offset in the signal. This offset varies from pixel to pixel, creating a pattern of noise that is fixed in the image. |
Another source of noise is the thermal noise (also called kTC noise) that is introduced by the reset transistor. This noise is random and varies from one readout to the next. It can be as large as the signal itself, making it difficult to extract the barcode information. |
A patent from a CMOS image sensor manufacturer explains the problem: 'A CMOS image sensor comprises a pixel section where unit pixels (pixel units) including a photodiode are arranged in a matrix, a scanning circuit for scanning unit pixels in order, and a correlated double sampling (CDS) circuit for processing signals output from the pixel section' . The CDS circuit is the key to overcoming these noise sources. |
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Chapter 2: The Principle of Correlated Double Sampling |
Correlated Double Sampling (CDS) is a technique that cancels the noise introduced by the reset operation. It works by taking two samples of each pixel: one immediately after reset (the reset level) and one after the integration period (the signal level). The reset level contains the reset noise and the fixed-pattern offset. The signal level contains the signal plus the same reset noise and offset. By subtracting the reset level from the signal level, the noise is canceled, leaving only the true signal. |
A Texas Instruments patent describes the principle succinctly: 'Correlated double sampling (CDS) generally refers to a sampling technique in which the strength of a signal at a node is determined as a difference of a strength at the node when the signal is coupled to the node and a strength at the node when the signal is decoupled from (or in general, not provided to) the node. CDS is often employed when the node may contain unknown non-signal components which can be treated as an offset or low frequency noise' . |
The patent elaborates on the application: 'As an example, correlated double sampling is often employed in imaging systems that use charge coupled devices (CCD) as the image sensors. Before the charge of each pixel is transferred to an input node of a charge-to-voltage converter receiving the charge output by the CCD, the output node is reset to a reference value. The reference value is then sampled (first sampling interval). The pixel charge is then transferred to the output node, and the output node is sampled again (second sampling interval). The first sample is subtracted from the second sample, with the difference (voltage or current) representing the charge collected by the pixel' . |
The subtraction of the two samples cancels the reset noise and the fixed-pattern offset, leaving only the signal. This is the essence of CDS. |
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Chapter 3: The Basic CDS Circuit |
The basic CDS circuit consists of a pair of capacitors, a set of switches, and an operational amplifier. The circuit samples the reset level onto one capacitor and the signal level onto another capacitor. It then subtracts the two voltages using the amplifier. |
A CMOS image sensor patent describes a typical CDS circuit: 'The CDS circuit 60 includes a first capacitor C1, a second capacitor C2, a power source VREF for generating a reference potential Vref, amplifiers AMP1 and AMP2 for amplifying signals, a switch SW1, being a switching element, for controlling connection with the unit pixel 11, a switch SW2, being a switching element, for connecting one end of the second capacitor C2 to the first capacitor C1 and power source VREF, and a switch SW3, being a switching element, for outputting output signals to an output bus' . |
The operation of this circuit follows a specific sequence: 'First, a selection signal SLCT1 for selecting pixels in the first row is turned to ON... Then a reset signal RST1 for resetting pixels in the first row is kept 'H' for a certain period of time to perform the first reset... After the reset time has ended, the reset signal RST1 is turned to 'L'. Therefore, the photodiode D1 begins integration according to the intensity of light' . |
The patent details the sampling operation: 'By turning the switch SW2 and switch SW1 in the CDS circuit 60 located for each column to ON, detected signals according to the time interval during which the photodiode D1 integrates are accumulated as electric charges not only in the first capacitor C1 but also in the second capacitor C2' . After this, the switches are turned OFF, holding the sampled signals. |
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Chapter 4: The Two-Step Sampling Process |
The CDS process is a two-step sampling operation. In the first step, the reset level is sampled. In the second step, the signal level is sampled. The difference between these two samples is the true signal. |
A patent from a CMOS image sensor manufacturer describes the process: 'A reset signal RST is turned to 'H' and then is turned to 'L'. By doing so, a photodiode (D1) begins integration according to the intensity of light. This detected signal is sent to a CDS circuit (20). A switch SW1 and a connection switch for sampling (21) in the CDS circuit (20) are turned ON to accumulate the detected signal according to integration time in parallel capacitors C1 and C2 as electric charges' . |
The reset level sampling is described: 'After a certain period of time has elapsed, the SW1 and connection switch for sampling (21) are turned OFF to hold the detected signal sampled. Next, the RST is turned again to 'H' and the SW1 is turned ON. Then the RST is turned to 'L' and the SW1 is turned OFF. By doing so, reset noise is sampled and held in the capacitor C1' . |
The result of this two-step process is that 'a pure signal component can be extracted from the detected signal' . The reset noise, which is common to both the reset and signal samples, is canceled. |
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Chapter 5: The Challenge of Reference Voltage Shift |
A significant challenge in CDS circuit design is the reference voltage shift. When the sampling switches are turned OFF, the voltage at the reference node can shift due to parasitic capacitance. This shift can cause differences in brightness among the pixels, degrading the image quality. |
The CMOS image sensor patent explains the problem: 'When the switch SW2 is turned OFF, the node potential on the reference voltage side, used as a reference, will shift by the influence of parasitic capacitance between the gate and source of a switching element, being the switch SW2, and between the gate and drain' . |
The patent further describes how this shift is exacerbated by the layout of the circuit: 'If the switching elements SW2-1 through SW2-8 are turned to OFF in that order, a shift in reference voltage will gradually become great due to fluctuations in the reference voltage, the wiring resistance of the reference voltage signal line 62, and the like. The dashed line in Fig. 7B indicates ideal reference voltage (reference potential Vref). An almost ideal reference voltage is obtained at SW2-1, but the reference voltage at SW2-8 is lower than the ideal reference potential (Vref) due to the influence of capacitance, wiring resistance, and the like' . |
This reference voltage shift is particularly problematic because it is amplified by the next stage: 'A shift in output signal caused by such a shift in the potential of a node on the reference voltage side is amplified by an amplifier located at the next stage of a CDS circuit. Therefore, even if a shift in signals output from a CDS circuit is small, differences in brightness will eventually arise among images' . |
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Chapter 6: Solutions to Reference Voltage Shift |
Several solutions have been developed to address the reference voltage shift problem. The CMOS image sensor patent describes a CDS circuit that reduces this shift by separating the sampling and reading functions of the switch. |
The patent explains the solution: 'A correlated double sampling circuit for processing signals output from a pixel section where, for example, image sensing devices are arranged in a matrix, is provided. This correlated double sampling circuit comprises a first capacitor for sampling and holding reset level signals corresponding to noise produced by resetting the pixel section, a second capacitor for sampling and holding detected signals obtained by a photoelectric conversion in the pixel section, a connection switch for sampling for controlling connection between a power' . |
By separating the sampling and reading functions, the circuit reduces the parasitic capacitance on the reference node, minimizing the voltage shift. This ensures that the reference voltage is stable across all columns, preventing the brightness variations that would otherwise occur. |
A Chinese patent describes another approach: a correlated double sampling integrating circuit that uses a negative feedback loop to control the node signals. The circuit includes 'a sampling and holding module, an energy storage unit and a feedback module; where the sampling and holding module is configured to perform sampling and holding for different input signals, the energy storage unit is configured to store charges corresponding to the input signals upon the sampling and holding to generate node signals (for example, node voltages), and the feedback module is configured to form a negative feedback loop with the energy storage unit to control node signals at an integrating stage to keep consistent with node signals at a resetting stage and prevent output jump' . |
This negative feedback loop ensures that the node signals at the integrating stage are consistent with those at the resetting stage, eliminating the output jump that would otherwise occur. |
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Chapter 7: The Integrating CDS Circuit |
A more advanced CDS circuit is the integrating type, which uses an integrator to accumulate the difference between the reset and signal samples. This approach provides additional noise reduction and gain. |
A Chinese patent describes a correlated double sampling integrating circuit with a feedback module that forms a negative feedback loop with the energy storage unit. The feedback module includes 'a first differential amplifier and a second differential amplifier' . The circuit uses inverse ON states of switch units to control the node signals at the resetting and integrating stages. |
The patent explains the operation: 'When the first switch unit is turned on and the second switch unit is turned off, the second differential amplifier and the first switch unit may form a first feedback loop with an energy storage unit (not shown in the changes), and the first differential amplifier and the second differential amplifier may form a second feedback loop with the energy storage unit, to control node signals generated by the energy storage unit at a resetting stage. When the first switch unit is turned off and the second switch unit is turned on, the energy storage unit forms a third feedback loop with the first differential amplifier to control node signals generated by the energy storage unit at an integrating stage' . |
This approach ensures that 'the correlated double sampling integrating circuit eliminates the noise caused by 1/f noise of the operational amplifier and noise caused by mismatch voltages, and prevents or weakens output jump of the correlated double sampling integrating circuit caused by the increase of the count of integrations' . |
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Chapter 8: Integrating CDS with Variable Gain |
A further innovation is the integration of CDS with a variable gain amplifier (VGA) in a single circuit. This reduces the power consumption and noise of the system by eliminating the need for a separate amplifier stage. |
A Chinese patent describes a correlated double sampling circuit and variable gain amplifier integrated circuit that uses a two-stage operational amplifier and capacitor arrays to achieve both functions. The circuit includes 'a first capacitor array CA and a second capacitor array CB' . The capacitor arrays are used to implement the variable gain function. |
The patent explains the advantages: 'The CDS (correlated double sampling circuit) and VGA (variable gain amplifier) integrated circuit improves the area and the power consumption of a system by avoiding usage of gain amplification in a VGA and meanwhile, obviously improve the signal to noise ration of the system by reducing noise induced by gain amplification' . |
By integrating the CDS and VGA functions, the circuit eliminates the need for a separate amplifier in the VGA stage, reducing both power consumption and noise. This is particularly important for barcode readers, where the signal-to-noise ratio is critical for reliable decoding. |
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Chapter 9: High-Frequency Noise Reduction |
In addition to reset noise and fixed-pattern noise, CDS circuits must also address high-frequency noise. This noise can be superimposed on the image sensor output signal and degrade the signal-to-noise ratio. |
A patent from Makoto Ohba describes a CDS circuit that reduces high-frequency noise by using a sampling capacitor divided into multiple portions . The circuit samples the input signal at multiple sampling points and averages the results. |
The patent explains: 'In a correlated double sampling circuit according to the invention, a sampling capacitor is equally divided into N portions (where N is an integer of at least 2) so that a feed-through portion of an image sensor output signal is sampled at N sampling points (where N is an integer of at least 2). The N portions of the sampling capacitor are connected in parallel with each other by an averaging switch, whereby an average value of a plurality of sampling values obtained by sampling is calculated' . |
This averaging technique reduces the high-frequency noise level. The patent notes: 'The averaging switch is added in order to calculate an average value of a plurality of sampling values obtained by the equally divided N portions of the sampling capacitor... Since the size of a sampling switch can be reduced to 1/N, the circuit area is almost the same as the conventional example. Moreover, since no other circuit is added, power consumption is not increased' . |
The circuit also includes 'a clock circuit for variably controlling a sampling frequency for sampling at a plurality of sampling points' . This allows the filter characteristics of the CDS circuit to be variably changed, adapting to different noise conditions. |
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Chapter 10: CDS Implementation in CMOS Image Sensors |
CMOS image sensors, which are increasingly used in barcode readers, implement CDS in the readout circuitry. The CDS circuit is typically located at the bottom of each column of pixels, processing the signals as they are read out. |
The CMOS image sensor patent describes a CDS circuit for each column: 'There is a CDS circuit 60 for each column in the pixel section. The CDS circuit 60 processes a signal output from a unit pixel in a row selected by the vertical scanning shift register from among unit pixels in a column to which the CDS circuit 60 is connected' . |
The CDS circuit includes 'a current source I1 [that] is provided to make the transistor M2 in the unit pixel 11 function as an amplifier' . This current source is essential for the operation of the pixel amplifier. |
The pixel itself consists of 'a photodiode D1, a reset transistor M1, a drive transistor M2, and a selection transistor M3' . This is the standard four-transistor (4T) pixel architecture used in most CMOS image sensors. |
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Chapter 11: The Timing of CDS Operation |
The timing of the CDS operation is critical for correct noise cancellation. The reset and sampling signals must be precisely timed to ensure that the reset and signal levels are correctly sampled. |
The CMOS image sensor patent provides a detailed timing description: 'First, a selection signal SLCT1 for selecting pixels in the first row is turned to ON by the vertical scanning shift register (the selection signal SLCT1 changes to the H level). Then a reset signal RST1 for resetting pixels in the first row is kept 'H' for a certain period of time to perform the first reset called an initial reset. During this time the potential on the cathode side of the photodiode D1 is VR (constant). After the reset time has ended, the reset signal RST1 is turned to 'L'. Therefore, the photodiode D1 begins integration according to the intensity of light' . |
The sampling sequence continues: 'By turning the switch SW2... and switch SW1 in the CDS circuit 60 located for each column to ON, detected signals according to the time interval during which the photodiode D1 integrates are accumulated as electric charges not only in the first capacitor C1 but also in the second capacitor C2. After a particular period of time has elapsed, the switch SW1 and switches SW2-1 through SW2-8 are turned to OFF to hold the detected signals sampled' . |
Then, 'the reset signal RST1 is turned to and kept 'H' for a certain period of time to perform a second reset and the switch SW1 is turned to ON during this time. By doing so, reset noise is accumulated in the first capacitor C1. After a predetermined period of time has elapsed, the switch SW1 is turned to OFF' . |
The result is that 'the potential at node VC2 of the second capacitor C2 is given by the following expression (1): Vref-((detected signal + reset noise)-reset noise)' . This is the pure signal component. |
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Chapter 12: The Next Stage Amplification |
The output of the CDS circuit is typically fed into a variable gain amplifier (VGA) for further amplification. The VGA amplifies the signal to a level suitable for the analog-to-digital converter (ADC). |
The Chinese patent on integrated CDS/VGA notes that 'the key factor that limits [signal to noise ratio] is noise. Poisson noise, fixed pattern noise and to read noise be three Main Noise Sources in CCD photoelectric conversion process, because can being exaggerated, prime noise is transferred to rear class, therefore the key that improves the signal to noise ratio of picture signal is the noise suppressing in AFE (analog front end) treatment system, due to the signal autocorrelation characteristic of reset noise, correlated-double-sampling (CDS) becomes and the most effectively suppresses means' . |
The amplification stage must be designed with low noise to avoid degrading the signal-to-noise ratio. The integrated CDS/VGA circuit addresses this by eliminating a separate amplifier in the VGA, reducing noise. |
Chapter 13: CDS and the Barcode Reader Signal Chain |
In a barcode reader, the CDS circuit is part of the analog front end (AFE). The AFE conditions the signal from the image sensor before it is digitized and decoded. |
The signal chain typically includes the image sensor, the CDS circuit, a variable gain amplifier, and an analog-to-digital converter. The CDS circuit removes reset noise and fixed-pattern noise. The variable gain amplifier adjusts the signal amplitude. The ADC digitizes the signal for the decoder. |
The quality of the CDS circuit directly affects the performance of the barcode reader. If the CDS circuit does not effectively cancel the noise, the decoded barcode data may contain errors. This is why CDS is an essential component of high-performance barcode readers. |
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Chapter 14: CDS on Glass for Large-Area Sensors |
Recent research has extended the CDS concept to sensors implemented on glass substrates. This is relevant for large-area imaging applications, such as flat-panel X-ray detectors. |
A research paper from a university describes 'a novel correlated double sampling (CDS) circuit, which can be implemented on glass by only using TFTs and capacitors. Thus, the readout voltage variation due to the threshold voltage shift under same light intensity illumination can be eliminated' . |
This work demonstrates the versatility of the CDS concept. It is applicable to any image sensor technology, from silicon CMOS to TFT-based sensors on glass. |
The paper notes that 'promoting the sensing accuracy of the image pixel sensor has become a hot issue. For voltage type active pixel sensor (V-APS), the readout voltage, as well as the sensing signal, will be affected by the thin film transistors (TFTs) characteristic variation, especially the shift in threshold voltage (Vth)' . CDS cancels this variation, improving the sensing accuracy. |
Chapter 15: Texas Instruments' Improved CDS Technique |
Texas Instruments has developed an improved CDS technique that reduces noise power at the amplifier output. The technique uses capacitors with different values to minimize the contribution of the sampling circuit to the total noise. |
The Texas Instruments patent describes a circuit where 'a first capacitor is charged to the first voltage in a first phase. A second capacitor is then charged to the second voltage in a second phase. In a third phase, the first capacitor is coupled to the input terminal of the amplifier and the second capacitor is coupled between the input and output terminals of the amplifier to cause the amplifier to generate the difference of the first and second voltages' . |
The key innovation is that 'the first capacitor has a capacitance much less than the second capacitor, thereby minimizing the noise power at the output of the amplifier, and requiring smaller implementation area' . |
This technique addresses the noise introduced by the sampling capacitors themselves. By making the first capacitor much smaller than the second, the noise contribution of the first capacitor is reduced. |
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Chapter 16: The Variable Sampling Frequency |
The Makoto Ohba patent introduces a variable sampling frequency for the CDS circuit. This allows the circuit to adapt to different noise conditions by changing the sampling rate. |
The patent describes a 'clock circuit for variably controlling a sampling frequency for sampling at a plurality of sampling points. Since the sampling frequency is variably controlled, filter characteristics of the correlated double sampling circuit can be variably changed and a frequency band to be reduced can be variable changed' . |
This is particularly useful for barcode readers, where the noise characteristics of the image sensor may vary with lighting conditions and other factors. By adapting the sampling frequency, the reader can maintain optimal noise rejection. |
Chapter 17: Advantages of CDS |
Correlated double sampling offers several advantages for barcode readers: |
1. Reset noise cancellation: CDS cancels the reset noise (kTC noise) that is introduced when the pixel is reset. This noise can be as large as the signal itself, so canceling it is essential for accurate reading. |
2. Fixed-pattern noise reduction: CDS cancels the fixed-pattern offset that varies from pixel to pixel. This reduces the fixed-pattern noise that would otherwise appear as a fixed pattern in the image. |
3. Low-frequency noise reduction: CDS also reduces low-frequency noise, such as 1/f noise, that can degrade the signal-to-noise ratio. |
4. Improved signal-to-noise ratio: By canceling these noise sources, CDS significantly improves the signal-to-noise ratio of the image sensor output. |
5. Integration with VGA: CDS can be integrated with a variable gain amplifier, reducing power consumption and board space. |
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Chapter 18: The Future of CDS |
The future of CDS in barcode readers is likely to involve greater integration and more sophisticated noise reduction techniques. The integration of CDS with VGA and ADC on a single chip will reduce the size and power consumption of the analog front end. |
The use of multiple sampling points and averaging will further reduce high-frequency noise. The adoption of digital CDS, where the subtraction is performed in the digital domain, may offer additional flexibility. |
The research on CDS on glass suggests that the technique will be applicable to new sensor technologies, opening up new applications for barcode reading. |
Chapter 19: Summary --- Correlated Double Sampling in Perspective |
Correlated double sampling is an essential technique for image sensors in barcode readers. It cancels the reset noise and fixed-pattern noise that would otherwise corrupt the barcode signal, enabling accurate decoding. |
We have examined how different companies and technologies have approached the challenges of CDS: |
A CMOS image sensor patent describes the basic CDS circuit, including the two-step sampling of reset and signal levels. The patent addresses the challenge of reference voltage shift and provides a solution by separating the sampling and reading functions . |
A Chinese patent describes a correlated double sampling integrating circuit with a feedback module that forms a negative feedback loop with the energy storage unit, eliminating 1/f noise and mismatch voltage noise . |
Texas Instruments developed an improved CDS technique that uses capacitors with different values to minimize noise power at the amplifier output . |
A Chinese patent describes an integrated CDS and variable gain amplifier circuit, eliminating the need for a separate amplifier in the VGA and reducing power consumption and noise . |
Makoto Ohba developed a CDS circuit that reduces high-frequency noise by using a sampling capacitor divided into multiple portions and averaging the samples . |
A research paper describes a CDS circuit implemented on glass using TFTs and capacitors, demonstrating the versatility of the technique for large-area sensors . |
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The key lessons from our exploration are: |
CDS cancels reset noise and fixed-pattern noise. By sampling the reset level and the signal level and subtracting them, the common-mode noise is canceled. |
CDS operates in two steps. The reset level is sampled first, then the signal level. The difference between these two samples is the true signal. |
Reference voltage shift is a challenge. When the sampling switches are turned OFF, the reference voltage can shift due to parasitic capacitance. This can cause differences in brightness among pixels. |
Solutions exist for reference voltage shift. These include separating the sampling and reading functions, using negative feedback loops, and integrating CDS with VGA. |
High-frequency noise can be reduced by averaging. By dividing the sampling capacitor and averaging the samples, the high-frequency noise is reduced. |
CDS is essential for barcode readers. It provides the clean, noise-free signal that is needed for reliable barcode decoding. |
In the end, correlated double sampling is a testament to the power of simple subtraction. It is a technique that takes two noisy samples and, by subtracting one from the other, extracts a clean signal. This is the foundation of high-performance image sensor readout, and it is essential for the accurate decoding of barcodes. The art of CDS lies in the careful design of the sampling circuit, ensuring that the reset and signal levels are accurately captured and subtracted, with minimal noise contribution from the circuit itself. |
cs@easiersoft.com